In some applications a buck controller is used in the power supply for a central processing unit (CPU). Most modern CPU integrated circuits (ICs) use some form of voltage control to regulate power dissipation; the CPU's voltage is lowered to conserve power and increased when higher performance is desired. The CPU may signal the power supply controller by supplying a voltage identification (VID) setting indicating a desired power supply voltage. In a buck regulated power supply, the buck controllers must control the output voltage in response to a change in VID settings. Many buck controllers rely on a current limit to control the maximum output current in response to a new VID setting. Other buck controllers use a digital up/down counter to slew the reference voltage at a controlled rate to change the output in response to a new VID setting.
Buck controllers are required to limit the output current when the reference voltage changes, for example, at start-up when the reference voltage first comes up or in some instances during normal operation. During normal operation, a CPU controller may change a VID setting to modify the output voltage. The VID setting may change depending on the power supply requirements of the CPU. When the CPU is idle, the voltage may be lowered to conserve power. During intensive CPU use, it is desirable to have the full processor voltage as this yields the best performance.
The requirement at start-up is handled by “soft start”. Two techniques are generally used for soft start. In one case, the slew rate of the reference voltage is limited after power is turned on with a soft start capacitor. In the second case, the soft start relies on the power supply controller's current limit. After start-up is complete, most converters rely on the power supply controller's current limit to control the output current during VID transitions. This may not be desirable because of the high currents that result every time a VID transition occurs.
The other problem with most CPU power supply controllers is the previously discussed passive droop. It is often desirable to correct for passive “droop” in the sensing voltage in these applications. Passive droop in the sensing voltage is caused by load current flowing in printed circuit board (PCB) trace resistance. If the sense voltage measuring the output voltage droops due to the flow of load current, then the output voltage will vary as the load current changes.
The feedback voltage (sensing voltage) for the power supply controller generally cannot be taken directly at the output close to the output filter capacitors because of stability concerns. The stability concerns are caused by the low equivalent series resistance (ESR) of the network of parallel ceramic capacitors used for the output filter. Therefore, feedback is generally taken a point “upstream” from the filter capacitors. Since load current flows through the PCB traces, any resistance resulting from sensing upstream results in a voltage drop. Since this resulting voltage drop is not inside the feedback loop, the controller cannot correct for these voltage drops. The output voltage droops as a fiction of load current creating a load regulation error. Sometimes this load regulation error is desirable, however, because the PCB trace resistance is unpredictable this may not be the best way to introduce intentional voltage droop. Passive droop may also result from a difference in ground potentials for different circuits. The ground potential for the bandgap reference in the power supply control chip is not necessarily at the same potential as the ground potential for the load. This is especially true in high current applications where the voltage drop in PCB traces may be significant. Therefore, to insure the best accuracy, the control loop should be able to correct for passive voltage droop. If a voltage droop is desired, then active circuits that do not suffer from the tolerance of the PCB trace resistance may be used to introduce it intentionally.
A typical constant ON-time controller for a buck regulator is shown in FIG. 5. The output voltage (Vout) 516 is set by the duty cycle which is defined as the ratio of ON-time of the high side field effect transistor (FET) 507 to the total switching time period. Whenever Vout 516 drops below the reference voltage Vref 517, comparator 508 sets latch 509. Gate drivers 519 turn ON FET 507 thereby charging inductor (L) 504 and delivering current to the load (not shown) coupled to Vout 516. Latch 509 remains set until the voltage 518 across capacitor (C) 511 exceeds Vref 517. Then, comparator 510 resets latch 509 and gate drivers 519 turn FET 507 OFF and FET 506 ON. The energy stored in L 504 causes the load current to continue to flow to Vout 516. Catch diode (D) 505 insures that the current in L 504 is not interrupted during switching to minimize transients.
The ON-time (time FET 507 is ON) is a function of both Vin 515 and Vref 517. As Vin 515 rises, the ON-time will be shorter since C 511 charges faster. If Vref 517 is increased, C 511 has to charge to a higher voltage to trip the comparator 510, also resulting in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 515 and Vout 516. To increase the current in inductor (L) 504 in response to a step change in the load (not shown) coupled to Vout 516, the control loop generates more ON pulses per unit time. To decrease the current in L 504, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant.
FIG. 1 is a schematic of a buck converter system 100 according to the prior art. A controller 110 receives Vout 120 and Vref 123 and generates output 130 for controlling gate drivers 109. Gate drivers 109 control the ON and OFF times of FET 106 and FET 107. Gate drivers 109 turn ON FET 107 thereby charging L 104 and delivering current to the load (not shown) coupled to Vout 120. Correspondingly, gate drivers 109 turn OFF FET 107 and turn ON FET 106 in response to output 130 of controller 110. The energy stored in L 104 causes the current to continue to flow to Vout 120 when FET 107 turns OFF and FET 106 turns ON. Catch diode D 105 insures current in L 104 is not interrupted to minimize transients during switching. Resistor (R) 103 represents resistance between L 104 and a load (not shown) coupled to Vout 120. Resistance 102 represents the equivalent series resistance (ESR) of capacitor C 101.
FIG. 1 shows a buck converter system 100 that uses an oscillator 111, an up/down counter 112, a digital to analog converter (DAC) 113, and a comparator 114, to control the output current during start up and during changes in the VID inputs 126. The bandgap reference 119 is amplified ((R 117+R 118)/R117) to the desired voltage by the non-inverting operational amplifier (OPA) 118. Reference DAC 115 may be a simple resistor divider with multiple taps. The VID inputs 126 determine which tap is used to generate Vref 121. At power up Vref 121 may rise quickly. Comparator 114 switches if Vout 120 is lower than Vref 121, and its output 122 then transitions to a logic one signaling a count-up command to the up/down counter 112. Up/down counter 112 counts each edge of the oscillator clock (OSC) 111. Thus, DAC 113 inputs increment up from zero in small increments providing slew rate limiting and preventing output current overshoot. The slew rate is determined by the step size of DAC 113 and the frequency of OSC 111. System 100 handles changes in the VID 126 setting. If the change in the VID inputs 126 requires a lower output voltage (Vref 121 is lower than Vout 120), then comparator 114 will transition to a logic zero signaling a countdown command to the up/down counter 112. In this case, Vout 120 will be stepped down slowly preventing output current under shoot.
The prior art system in FIG. 1 does not correct for DC errors between the ground potential of the reference DAC 115 (e.g., low side of R2117) and the ground potential of Vout 120 (negative terminal of C1101). One way to solve this problem is to tie the ground for reference DAC 115 directly to the negative side of C1101. This forces the two ground potentials to be equal. However, it is not always possible to locate the bandgap reference 119 and reference DAC 115 close to Vout 120. Therefore, there is a need to generate a remote reference that may not be referenced to the same ground as Vout 120 when providing a VD programming function. If a remote reference is used, there is also a need to compensate for any DC offset that may result. There is also a need for providing slew rate limiting of the remote reference so that the output current does not overshoot or undershoot while programming Vout 120 and without having the need for a counter 112, DAC 113 and oscillator 111. There is, therefore, a need for circuitry to generate a compensated reference voltage to control the slew rate of the output current of a buck converter power supply in response to load changes and to changes in the regulated output voltage due to VID programming. There is also a need to have the compensated reference voltage reduce offset errors due to current flow in PCB traces.